1. Field of the Invention
The present invention relates to a semiconductor device having a MOS structure and a method of manufacturing the semiconductor device, and more particularly to an improvement for connecting portions provided at a comparatively short distance which are to be connected by a wiring while reducing a wiring capacity.
2. Description of the Background Art
First of all, terms used in this specification will be described. In the specification, xe2x80x9ca MOS (Metal Oxide Semiconductor) FETxe2x80x9d or xe2x80x9ca MOS structurexe2x80x9d widely includes those having a gate electrode constituted by a conductor other than metals following a custom of this field. In the specification, moreover, a set of xe2x80x9ca source regionxe2x80x9d and xe2x80x9ca drain regionxe2x80x9d will be referred to as xe2x80x9ca source/drain regionxe2x80x9d.
There has been known the fact that a lamination structure having a polysilicon film and a metal film is effectively used as a gate electrode in place of a conventional lamination structure having a polysilicon film and a metal silicide film in order to reduce a resistance of a gate electrode of a semiconductor element (for example, a MOSFET) having a MOS structure to implement a high-speed operation when a semiconductor integrated circuit is to be manufactured. However, in the case where a metal film is used for the gate electrode, the conditions of a heat treatment are restricted for reasons of a heat resistance after the gate electrode is formed. Accordingly, it is usually necessary to drop a heat treating temperature in the heat treatment of a source/drain region to be formed after the gate electrode is formed.
As a result, there has been a problem in that the source/drain region is insufficiently activated to raise a source/drain resistance, resulting in a reduction in the driving capability of the MOSFET. Furthermore, also in the case where a tantalum oxide film is used for a gate insulating film, for example, the restrictions on the heat resistance are not removed but the same problem related to the source/drain resistance arises. In order to solve the problem, there has been proposed a method for forming a dummy gate electrode to form a source/drain before a gate electrode is formed.
As an example, FIGS. 19 to 26 show a semiconductor device and a method of manufacturing the semiconductor device which have been disclosed in the Document xe2x80x9cExt. Abst. of International Electron Devices Meeting (1998) pp. 785 to 788xe2x80x9d. A semiconductor device 151 having a sectional structure shown in FIGS. 19 and 20 comprises a MOSFET having a metal gate electrode constituted by a replace method using a dummy gate electrode. FIG. 19 illustrates a sectional structure taken along a cutting line Axe2x80x94A or a cutting line Bxe2x80x94B in FIG. 20.
In the semiconductor device 151, a plurality of element regions are set in a main surface of a semiconductor substrate 51 made of single crystal silicon and a MOSFET is built in each of the element regions. An element isolating film 52 is selectively formed as a trench type element isolating region in an area between the element regions in the main surface of the semiconductor substrate 51. The semiconductor substrate 51 and the element isolating film 52 are covered with an insulating layer 57 acting as a mold.
Openings 71 and 72 penetrating from an upper surface to a lower surface are selectively provided on the insulating layer 57. A gate insulating film 53 is formed on a portion in the main surface of the semiconductor substrate 51 which is surrounded by the opening 71, and a gate electrode 61 is provided on the gate insulating film 53 to fill in the opening 71. A gate electrode 65 is buried in the opening 72 formed on the element isolating film 52. The gate electrodes 61 and 65 are formed of the same metal.
For each of the element regions, the semiconductor substrate 51 is provided with a channel region 55 selectively exposed to the main surface and a pair of source/drain regions 70 (or 70a) selectively exposed to the main surface with the channel region 55 interposed therebetween. The channel region 55 is opposed to the gate electrode 61 (or 65) through the gate insulating film 53. Moreover, the gate insulating film 53 and the element isolating film 52 are connected integrally with each other. The gate electrodes 61 and 65 are provided across both of the gate insulating film 53 and the element isolating film 52.
The insulating layer 57 and the gate electrodes 61 and 65 are covered with an upper insulating layer which is not shown. The source/drain regions 70 and 70a and the gate electrodes 61 and 65 are connected to an upper wiring layer (not shown) through a contact hole 75 which is selectively provided in the upper insulating layer.
FIGS. 21 to 26 are views showing the steps of a method of manufacturing the semiconductor device 151. In order to manufacture the semiconductor device 151, first of all, the step of FIG. 21 is executed. At the step of FIG. 21, a semiconductor substrate 51 made of single crystal silicon which has a main surface is first prepared. Next, a trench type element isolating film 52 is selectively formed in the main surface of the semiconductor substrate 51. The element isolating film 52 is an insulating film for isolating elements. Then, boron ions are implanted into the main surface of the semiconductor substrate 51. Consequently, a well is formed and doping for threshold voltage regulation is carried out at the same time.
At the step of FIG. 22, subsequently, a thermal oxidation treatment is first carried out. Consequently, an insulating film 82 which is a silicon oxide film is formed on the main surface of the semiconductor substrate 51. Then, a polysilicon film and a silicon nitride film are deposited on the insulating film 82 and the element isolating film 52 by using a CVD (Chemical Vapor Deposition) method. Next, the polysilicon film and the silicon nitride film are subjected to patterning by using photolithography and anisotropic etching. Consequently, a conductive layer 54 and an insulator 55 are formed. As will be described below, the conductive layer 54 and the insulator 55 serve as dummy gate electrodes.
At the step of FIG. 23, next, arsenic ions are selectively implanted into the main surface of the semiconductor substrate 51 by using the conductive layer 54 and the insulator 55 as shields. Consequently, a pair of source/drain regions 70 selectively exposed to the main surface are formed. A portion which is interposed between the pair of source/drain regions 70 and is selectively exposed to the main surface under the conductive layer 54 corresponds to a channel region 55.
At the step of FIG. 24, first of all, a heat treatment is carried out so that a dopant introduced into the source/drain region 70 is activated. Subsequently, the insulating film 82 is selectively removed to cause the portion provided under the conductive layer 54 to remain as a gate insulating film 83. Then, the CVD method is executed. Consequently, a silicon oxide film is deposited over the whole upper surface of a product obtained in this stage. Subsequently, a CMP (Chemical Mechanical Polishing) method is executed. Thus, the silicon oxide film is polished until an upper surface of the dummy gate electrode, that is, an upper surface of the insulator 55 is exposed. As a result, an insulating layer 57 having an upper surface flattened is formed as shown in FIG. 24. The insulating layer 57 selectively defines an opening 71. The conductive layer 54 and the insulator 55 are buried in the opening 71. An upper surface of the insulating layer 57 is arranged on a level with that of the insulator 55.
At the step of FIG. 25, subsequently, the conductive layer 54 and the insulator 55, that is, the dummy gate electrodes are removed. At this time, the gate insulating film 83 is simultaneously removed as shown in FIG. 25. The insulating layer 57 having the opening 71 cavitated serves as a mold.
At the step of FIG. 26, first of all, thermal oxidation is executed. Consequently, a gate insulating film 53 is formed as a silicon oxide film on a portion in the main surface of the semiconductor substrate 51 which is exposed to the opening 71. Then, tungsten is deposited to fill in the opening 71 and to cover the upper surface of the insulating layer 57 by using the CVD method or a sputtering method. As a result, a metal layer 60 is formed.
Thereafter, the CMP method is executed to flatten an upper surface of the metal layer 60. Consequently, the metal layer 60 is caused to remain as a gate electrode 61 only in the opening 71 of the insulating layer 57 acting as the mold. Thus, the structure shown in FIG. 19 is completed.
In order to implement a predetermined integrated circuit, it is necessary to selectively connect a plurality of gate electrodes 61 and 65 and a plurality of source/drain regions 70 and 70a. For this purpose, it is necessary to form a contact hole in a part corresponding to a portion provided over the gate electrode and the source/drain region which are to be connected in the insulating layer including the insulating layer 57 which is provided over the main surface of the semiconductor substrate 51 and to bury a wiring material in the contact hole, thereby performing a connection.
In the semiconductor device 151, however, a material and a height of an upper surface (that is, a distance from the main surface of the semiconductor substrate) is varied between the gate electrodes 61 and 65 and the source/drain regions 70 and 70a. Accordingly, it is necessary to provide the contact hole on a plurality of members having various materials and different heights of upper surfaces by using dry etching. However, such a technique has become more difficult with the progress of microfabrication of a semiconductor device in recent years.
In order to solve the above-mentioned problem, for example, Japanese Laid-Open Patent Publication No. 9-293862 has proposed a method for simultaneously forming a plug communicating with a source/drain region when removing a dummy gate electrode and forming a gate electrode by a metal layer, thereby making materials and heights of upper surfaces identical to each other between the plug and the gate electrode. In this method, a contact hole to be positioned above the gate electrode and the source/drain region can be formed on members having materials and heights of upper surfaces which are common. FIG. 27 is a sectional view showing a structure of a semiconductor device thus constituted.
Also in a semiconductor device 152 shown in FIG. 27, a plurality of element regions are set in a main surface of a semiconductor substrate 51 made of single crystal silicon in the same manner as the semiconductor device 151 and a MOSFET is built in each of the element regions. The arrangement of the element regions is illustrated in the same manner as in FIG. 20, for example. In the semiconductor device 152, gate electrodes 62 and 63 are buried in openings 71 and 72 provided in an insulating layer 57, respectively. Both the gate electrodes 62 and 63 constitute a lamination structure having a conductive layer 54 made of polysilicon and a metal layer 76 formed on the conductive layer 54.
Moreover, a side wall 56 is formed on side faces of each of the gate electrodes 62 and 63. The openings 71 and 72 also accommodate the side wall 56 therein. As will be described later, the insulating layer 57 and the side wall 56 function as molds in a manufacturing process.
Furthermore, the insulating layer 57 is selectively provided with an opening 73 penetrating from an upper surface to a lower surface over a source/drain region 70. A metal layer 78 made of the same material as a material of the metal layer 76 is buried in the opening 73. The metal layer 78 functions as a plug for electrically connecting the source/drain region 70 to other portions.
FIGS. 28 to 32 are views showing the steps of a method for manufacturing the semiconductor device 152. In order to manufacture the semiconductor device 152, first of all, the step of FIG. 21 is executed and the step of FIG. 28 is then executed. At the step of FIG. 28, a thermal oxidation treatment is first carried out. Consequently, an insulating film 88 which is a silicon oxide film is formed on a main surface of a semiconductor substrate 51. Then, a polysilicon film, a silicon oxide film and a polysilicon film are deposited on the insulating film 88 and an element isolating film 52 in this order by using a CVD method.
Next, these films are subjected to patterning by using photolithography and anisotropic dry etching. Consequently, a conductive layer 54, an insulator 59 and a conductive layer 86 which constitute a three-layer structure are formed. As will be described later, the insulator 59 and the conductive layer 86 serve as dummy gate electrodes. Then, impurity ions are selectively implanted into the main surface of the semiconductor substrate 51 by using the three-layer structure as a shield. Consequently, a pair of LDD (Lightly Doped Drain) regions (not shown) selectively exposed to the main surface are formed.
At the step of FIG. 29, first of all, the insulating film 88 is selectively removed to cause a portion provided under the conductive layer 54 to remain as a gate insulating film 53. Then, a side wall 56 is formed on a side face of the three-layer structure. Subsequently, arsenic ions are selectively implanted into the main surface of the semiconductor substrate 51 by using the three-layer structure and the side wall 56 as shields. Consequently, a pair of source/drain regions 70 are formed.
At the step of FIG. 30, next, the CVD method is executed to deposit a silicon oxide film over the whole upper surface of a product obtained in this stage. By executing a CMP method, subsequently, the silicon oxide film is polished until an upper surface of the dummy gate electrode, that is, an upper surface of the conductive layer 86 is exposed. As a result, an insulating layer 84 having an upper surface flattened is formed as shown in FIG. 30. The insulating layer 84 selectively defines openings 71 and 72. The conductive layer 54, the insulator 59 and the conductive layer 86 are buried in the openings 71 and 72. The upper surface of the insulating layer 84 is arranged on a level with that of the conductive layer 86.
At the step of FIG. 31, subsequently, the insulator 55 and the conductive layer 86, that is, the dummy gate electrodes are removed by dry etching or wet etching. At the same time, an opening 73 penetrating from an upper surface to a lower surface is selectively formed in a portion of an insulating layer 57 which is provided on the source/drain region 70. The insulating layer 57 having the opening 73 and the openings 71 and 72 from which the dummy gate electrodes are removed serves as a mold at the next steps.
At the step of FIG. 32, first of all, a titanium nitride film (not shown) is deposited as a barrier metal over the whole upper surface of a product obtained in this stage. Then, tungsten is deposited on the barrier metal by using a CVD method. Consequently, a metal layer 60 is formed. The metal layer 60 is formed to fill in the openings 71, 72 and 73 and to cover an upper surface of the insulating layer 57.
Then, the CMP method is executed to flatten an upper surface of the metal layer 60. As a result, the metal layer 60 is caused to remain as a metal layer 76 or 78 only in the openings 71, 72 and 73 of the insulating layer 57 acting as the mold. Thus, the structure shown in FIG. 27 is completed.
As shown in FIG. 27, in the semiconductor device 152, upper surfaces of gate electrodes 62 and 63 and an upper surface of the metal layer 78 acting as a plug which is positioned on the source/drain region 70 have the same height from the main surface of the semiconductor substrate 51 and are formed of the same metallic material. Accordingly, a difficulty in forming a contact hole which has been a trouble of the semiconductor device 151 can be eliminated.
However, the semiconductor device 152 is similar to the semiconductor device 151 in that a plurality of portions such as a plurality of gate electrodes, plural pairs of source/drain regions and the like should be selectively connected through a wiring material buried in a contact hole 75 as shown in FIG. 33 in order to implement a predetermined integrated circuit. For this reason, portions which are mutually positioned at a short distance have also been connected in a bypassing configuration through the wiring material buried in the contact hole 75 and a first wiring layer M1 positioned on a first layer (a lowermost layer). Consequently, there has been a problem in that a useless wiring delay is caused, resulting in a considerable delay on signal propagation.
In such a semiconductor device as to provide a DRAM having a high density and a mass storage capacity in the same semiconductor substrate, a height of a capacitor from the semiconductor substrate is set large in order to keep a capacity of the capacitor equal to or larger than a certain capacity. Consequently, an insulating layer provided between a wiring layer and the semiconductor substrate is set thick. As a result, a contact hole is provided deeply in the insulating layer. In such a semiconductor device, portions which are mutually positioned at a short distance are effectively connected through a remarkably long wiring. Consequently, a great wiring delay is particularly caused.
In recent years, furthermore, an integrated circuit has become complicated with an enhancement in functionality of a semiconductor device. As a result, multilayered wiring layers M1 to M5 have been used as illustrated in FIG. 33. Consequently, there has been a problem in that a manufacturing cost is increased.
If separate portions can be connected to each other at a height of a metal layer included in a gate electrode, both the problems of the wiring delay and the high cost caused by the multilayered interconnection can be eliminated at the same time . However, even if this is to be realized within the prior art, a gate electrode 65 is only extended over the source/drain region 70 together with a gate insulating film and a connection between the gate electrode 65 and the source/drain region 70 without a contact hole and the like cannot be achieved as shown in FIG. 34 illustrating an example of the semiconductor device 151.
In order to solve the above-mentioned problems of the conventional device, it is an object of the present invention to obtain a semiconductor device capable of reducing a wiring delay to suppress a signal delay and decreasing the number of wiring layers to reduce a manufacturing cost, and to provide a method suitable for manufacturing the semiconductor device.
In the same manner as in the above-mentioned Japanese Laid-Open Patent Publication No. 9-293862, there has been known Japanese Laid-Open Patent Publication No.11-26757 as a document which has disclosed a technique for forming a plug communicating with a source/drain region simultaneously with the formation of a gate electrode by a metal layer.
A first aspect of the present invention is directed to a semiconductor device comprising a semiconductor substrate defining a main surface, the semiconductor substrate including a channel region selectively exposed to the main surface for each of a plurality of element regions set along the main surface, and a pair of source/drain regions selectively exposed to the main surface with the channel region interposed therebetween, and the semiconductor device further comprising an insulating film selectively provided on the main surface and including a gate insulating film provided on the channel region for each of the element regions, a conductive layer provided on the insulating film, a first insulating layer which has a first opening divided into a plurality of portions and penetrating from an upper surface to a lower surface by accommodating the conductive layer and being selectively opened over the pair of source/drain regions for each of the element regions and which covers the main surface and the insulating film, a second insulating layer provided on the first insulating layer and formed of a material different from a material of the first insulating layer for selectively defining a second opening penetrating from an upper surface to a lower surface to communicate with the first opening, a third insulating layer provided on the second insulating layer and formed of a material different from a material of the second insulating layer for selectively defining a third opening which is opened to include the second opening and penetrates from an upper surface to a lower surface to cause at least one set included in the mutually separated portions of the first opening to communicate with each other, and a metal layer buried in the first to third openings together with the conductive layer.
A second aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, further comprising a fourth insulating film which is provided under the first insulating layer, selectively defines a fourth opening formed under the first opening and having the conductive layer and the metal layer buried therein and is formed of a material different from materials of the first and third insulating layers.
A third aspect of the present invention is directed to the semiconductor device according to the first or second aspect of the present invention, wherein the first insulating layer and the third insulating layer are formed of the same material.
A fourth aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of (a) preparing a semiconductor substrate defining a main surface, (b) forming an insulating film on the main surface, (c) depositing a conductive material to cover the insulating film, (d) patterning the conductive material, thereby selectively causing the conductive material to remain as a conductive layer to include a portion positioned above a channel region which is selectively set for each of a plurality of element regions set along the main surface, (e) selectively introducing an impurity into the main surface by using the conductive layer as a shield, thereby forming a pair of source/drain regions which are selectively exposed to the main surface with the channel region interposed therebetween for each of the element regions, (f) selectively removing a portion of the insulating film which is not covered with the conductive layer but is exposed in each of the element regions before the step (e) or after the step (e), (g) depositing a first insulating layer to cover the main surface, the insulating film and the conductive layer, (h) polishing the first insulating layer, thereby flattening an upper surface of the first insulating layer, (i) depositing a material which is different from a material of the first insulating layer to cover the first insulating layer and the conductive layer, thereby forming a second insulating layer, (j) patterning the second insulating layer, thereby forming a first opening which is divided into a plurality of portions to be selectively opened above the conductive layer and the pair of source/drain regions for each of the element regions and penetrates from an upper surface to a lower surface, (k) depositing a material which is different from a material of the second insulating layer to cover the first and second insulating layers and the conductive layer, thereby forming a third insulating layer after the step (j), (l) executing etching having etching selectivity for the first and third insulating layers against the second insulating layer and the conductive layer, thereby selectively forming, in the third insulating layer, a second opening penetrating from an upper surface to a lower surface to include the first opening and to connect at least one set contained in the portions of the first opening which are separated from each other, and selectively forming, in the first insulating layer, a third opening penetrating from an upper surface to a lower surface under the first opening, (m) depositing a metal layer to fill in the first to third openings and to cover an upper surface of the third insulating layer, and (n) polishing the metal layer until the third insulating layer is exposed.
A fifth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, further comprising the step of (c1) depositing, on the conductive material, an insulating material which is different from the material of the second insulating layer after the step (c) and before the step (d), the step (d) including the steps of (d-1) patterning the insulating material, thereby causing the insulating material to selectively remain as an insulator, and (d-2) performing selective etching by using the insulator as a shield, thereby forming the conductive layer, at the step (e), the insulator being also used as the shield together with the conductive layer, at the step (g), the first insulating layer being deposited to cover the insulator in addition to the main surface, the insulating film and the conductive layer, at the step (i), the second insulating layer being formed to cover the insulator in addition to the first insulating layer and the conductive layer, at the step (k), the third insulating layer being formed to cover the insulator in addition to the first and second insulating layers and the conductive layer, at the step (l), as said etching, etching having etching selectivity for the first and third insulating layers and the insulator against the second insulating layer being executed, thereby selectively forming, in the insulator, a fourth opening penetrating from an upper surface to a lower surface under the first opening in addition to the selective formation of the third opening on the first insulating layer, and at the step (m), the metal layer being deposited to fill in the fourth opening in addition to the first to third openings.
A sixth aspect of the present invention is directed to the method of manufacturing a semiconductor device according to the fourth or fifth aspect of the present invention, further comprising the step of (f1) depositing an insulating material different from materials of the first and third insulating layers to cover the main surface, the insulating film and the conductive layer, thereby forming a fourth insulating layer after the step (f) and before the step (g), at the step (g), the first insulating layer being deposited to cover the fourth insulating layer in addition to the main surface, the insulating film and the conductive layer, at the step (h), the polishing being executed until the fourth insulating layer is exposed, at the step (i), the second insulating layer being formed to cover the fourth insulating layer in addition to the first insulating layer and the conductive layer, at the step (j), the patterning being performed including a portion of the fourth insulating layer which is provided in contact with the second insulating layer, and at the step (k), the third insulating layer being formed to cover the fourth insulating layer in addition to the first and second insulating layers and the conductive layer, and the manufacturing method further comprising the step of (l1) selectively removing an exposed portion of the fourth insulating layer after the step (l).
A seventh aspect of the present invention is directed to the method of manufacturing a semiconductor device according to any of the fourth to sixth aspects of the present invention, wherein the first insulating layer and the third insulating layer are formed of the same material.
According to the first aspect of the present invention, the third opening defined by the third insulating layer is formed to cause at least one set of the portions included in the first opening and separated from each other to communicate with each other. Therefore, the metal layer which is buried in the third opening and also forms the gate electrode serves as a lowermost wiring layer. Consequently, it is possible to obtain an effect that a wiring delay can be reduced and the number of the wiring layers can be decreased resulting in a reduction in a manufacturing cost, due to the connection of close portions through an effectively short wiring, which have not been obtained by the technique disclosed in the Japanese Laid-Open Patent Publications Nos. 9-293862 or 11-26757.
According to the second aspect of the present invention, the fourth insulating layer is provided under the first insulating layer. Therefore, the fourth insulating layer can be used as an etching stopper when the first opening is to be formed in the first insulating layer in the manufacturing process. Consequently, it is possible to prevent a defective junction and the like from being caused by the inadvertent removal of a part of the insulating film even if a mask alignment makes errors.
According to the third aspect of the present invention, the first and third insulating layers are formed of the same material. Therefore, the opening can easily be formed in both of the first and third insulating layers at the same etching step. More specifically, the manufacturing process can further be simplified and a product can further be made inexpensive.
According to the fourth aspect of the present invention, the first opening is formed in the second insulating layer to be selectively opened above the conductive layer and a pair of source/drain regions for each of the element regions, the second opening is selectively formed in the third insulating layer to connect at least one set of the portions included in the first opening and separated from each other and the third opening penetrating from the upper surface to the lower surface of the first insulating layer under the first opening is selectively formed in the first insulating layer. Furthermore, these openings are filled with the metal layer. Consequently, the metal layer which is buried in the second opening and also forms the gate electrode serves as a lowermost wiring layer. Accordingly, it is possible to obtain an effect that a wiring delay can be reduced and the number of the wiring layers can be decreased resulting in a reduction in a manufacturing cost, due to the connection of close portions through an effectively short wiring, which have not been obtained by the technique disclosed in the Japanese Laid-Open Patent Publications Nos. 9-293862 or 11-26757.
According to the fifth aspect of the present invention, the conductor is subjected to selective etching by using the insulator as the shield so that a conductive layer is formed. In other words, there is an advantage that the insulator can be utilized as a hard mask in the formation of the conductive layer.
According to the sixth aspect of the present invention, the fourth insulating layer is formed before the formation of the first insulating layer. Therefore, when the third opening is to be formed in the first insulating layer, the fourth insulating layer functions as an etching stopper. Consequently, it is possible to prevent a defective junction and the like from being caused by the inadvertent removal of a part of the insulating film even if a mask alignment makes errors.
According to the seventh aspect of the present invention, the first and third insulating layers are formed of the same material. Therefore, the second and third openings can be formed more efficiently at the same etching step.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.